1. Field of the Invention
This invention relates generally to magnetic tunneling junction (MTJ) MRAMs and more particularly to the use of a simple fabrication process that leads to a smooth bottom electrode and superior performance properties.
2. Description of the Related Art
The magnetic tunneling junction device (MTJ device) is essentially a variable resistor in which the relative orientation of magnetic fields in an upper and lower magnetized electrode controls the flow of spin-polarized tunneling electrons through a very thin dielectric layer (the tunneling barrier layer) formed between those electrodes. As electrons pass through the lower electrode they are spin polarized by its magnetization direction. The probability of an electron tunneling through the intervening tunneling barrier layer then depends on the magnetization direction of the upper electrode. Because the tunneling probability is spin dependent, the current depends upon the relative orientation of the magnetizations of magnetic layers above and below the barrier layer. Most advantageously, one of the two magnetic layers (the pinned layer) in the MTJ has its magnetization fixed in direction, while the other layer (the free layer) has its magnetization free to move in response to an external stimulus. If the magnetization of the free layer is allowed to move continuously, as when it is acted on by a continuously varying external magnetic field, the device acts as a variable resistor and it can be used as a read-head. If the magnetization of the free layer is restricted to only two orientations relative to the fixed layer (parallel and anti-parallel), the first of which produces a low resistance (high tunneling probability) and the second of which produces a high resistance (low tunneling probability), then the device behaves as a switch, and it can be used for data storage and retrieval (a MRAM).
Magnetic tunneling junction devices are now being utilized as information storage elements in magnetic random access memories (MRAMs). Typically, when used as an information storage or memory device, a writing current orients the magnetization of the free layer so that it is either parallel (low resistance) or anti-parallel (high resistance) to the pinned layer. The low resistance state can be associated with a binary 0 and the high resistance state with a binary 1. At a later time a sensing current passed through the MTJ indicates if it is in a high or low resistance state, which is an indication of whether its magnetizations are, respectively, antiparallel or parallel and whether it is in a 0 or 1 state. Typically, switching the magnetization direction of the free layer from parallel to antiparallel and vice-versa is accomplished by supply currents to orthogonal conductor lines, one which is above the MRAM cell and one which is below it. The line below the cell is referred to as the word line and it is electrically isolated from the cell. The line above the cell, called the bit line, is in direct electrical contact with the cell and is used for both writing on the cell, ie changing the direction of the free layer magnetization and reading the cell, ie detecting the free layer magnetization direction. The two lines pass each other orthogonally, in separated vertical planes, with the cell lying between them. Thus their combined field peaks just above the switching threshold of the cell, the field required to cause a transition from parallel to antiparallel orientations of the free layer and pinned layer magnetizations.
For fast operation, the cell must have a high magnetoresistance ratio (DR/R), where DR represents the resistance variation when the free layer switches its magnetization direction and R represents the total minimum resistance of the cell. For stable operation, the cell's junction resistance, RA, where A is cell cross-sectional area, must be well controlled. When the MRAM device is used as the basic element of a memory, it is replicated to form an array of many such devices and integrated with associated CMOS circuitry which accesses particular elements for data storage and retrieval.
When fabricating an MRAM element or an array of such elements, the necessity of creating a high value of DR/R and maintaining a high degree of control over the junction resistance requires the formation of thin, smooth layers of high quality.
Slaughter et al. (U.S. Pat. No. 6,544,801 B1) teaches a method of fabricating such a magnetic tunneling device wherein the problem of interdiffusion between layers of different metals during high temperature annealing processes is significantly reduced. Such interdiffusion would adversely affect the properties of the various layers because of the tendency of the various metals to alloy with each other.
Dill et al. (U.S. Pat. No. 6,114,719) teaches a method of effectively biasing an MTJ device using biasing layers disposed within the device stack, so that its magnetic states are stable, yet there is not required the addition of adjacent magnetic structures which would adversely affect the high device density required for an MRAM array.
In a “standard process” MRAM array structure the MTJ stack (lower electrode/AlOx tunneling barrier/upper electrode) is deposited on top of the bottom conductor, which is typically a tri-layer such as Ta/Cu/Ta or NiCr/Ru/Ta. In the latter tri-layer, the Ta that caps the Ru is grown with an α-phase structure, in the former tri-layer, the Ta that caps the Cu is grown with a β-phase structure. Prior to depositing the MTJ stack it is necessary to sputter-etch the TaO which grows on the Ta capping layer. This sputter-etch not only removes the surface TaO, but the energetic Ar sputtering ions also alter the Ta surface structure. The resulting sputter-etched Ta surface appears to be “amorphous-like”, similar to that of amorphous Al2O3. In our experiments we have found that an altered Ta surface is necessary for forming a flat, smooth bottom electrode on which to most advantageously form an oxidized Al tunneling barrier layer of high integrity. It was also noted by us that refilling the sputter-etched Ta surface by a Ta sputter-deposition actually results in a rougher surface structure of the bottom electrode. The integrity of the oxidized Al barrier layer is an essential element in fabricating a high quality MTJ device.
Formation of a high-speed MRAM array is quite complicated. Normally its word line structure is surrounded by a dielectric layer, so the line essentially lies within a cavity. This cavity has a back (or bottom) surface and two parallel side surfaces that are spaced apart. The back and/or side surfaces of the cavity are covered with an NiFe magnetic layer which acts as a field keeper (it contains the magnetic flux). The conducting portion of the line, surrounded by the magnetic keeper structure, is formed within the cavity. A polishing process is then used to remove any portion of the keeper or conducting portion of the line that extends above the level of the dielectric surface and to generally render that surface planar.
A novel MRAM array structure, not using the conducting lead structure of the standard process, has been developed in which the word line is constructed on top of the MTJ. The MRAM configuration of this novel array structure is:    NiCr50/NiFe100/NiCr30/Cu50/MnPt100/CoFe18/Ru7.5/CoFe15/Al(8–10)/ROX/free/capThe NiCr50/NiFe100/NiCr30/Cu50 portion is the bottom conducting lead (the numerals representing thicknesses in angstroms), which includes a NiCr 50 seed layer, a100 angstrom NiFe soft adjacent keeper layer, a second NiCr 30 seed layer and a Cu 50 conducting layer; the MnPt100/CoFe18/Ru7.5/CoFe15 portion is the bottom electrode (a synthetic pinned structure), the Al(8–10)/ROX is a tunneling barrier layer formed by radical oxidation of an 8–10 angstrom thick Al layer and then there is the upper electrode, which includes a free layer and a capping layer formed thereon but not described here in detail. The entire stack is advantageously formed by magnetron sputtering in a single pump-down of the sputtering chamber.
In initial testing of this single pump-down fabrication, RA (junction resistance), DR/R and Vb (breakdown voltage of the barrier layer) were found to be much lower than values obtained from the standard (prior art) process in which the patterned conductor lead and the MRAM stack are formed separately. Further, high resolution TEM analysis of the single pump-down layers showed that the bottom electrode layers had a columnar grain structure, which tended to create rough surfaces. In contrast, the surfaces of layers formed in the standard process were relatively smooth and flat. The essential difference in the two processes is that the standard process configuration includes a Ta capping layer that is sputter-etched.
The object of this invention is to modify the single pump-down process so that a smooth, flat layered structure (as in the standard process) is obtained while still maintaining the advantages of the single pump-down of the novel process.